Si Nanowire Quantum-Dot Transistor

No high-res lithography

In-situ formation of quantum dots in Si nanowires via step-necked constrictions enables single-hole transistors without high-resolution lithography.

Shichang, Fan · Li, Songlin · Huang, Shaoyun · Wang, Junzhuan · Yu, Linwei

ACS Nano 2026

Specifications

Coulomb blockade operating temperature

{'zh': '40', 'en': '40'} K

QD island width

{'zh': '50', 'en': '50'} nm

Tunnel constriction size

{'zh': '10', 'en': '10'} nm

Advantages

No high-res lithography

Interfacial forces stretch the catalytic droplet at sharp convex corners when the nanowire grows across double-steps, naturally forming the quantum dot structure.

Works at 40 K

Quantum confinement in these step-necked constrictions is strong enough to control individual hole transport, with Coulomb blockade oscillations and diamonds persisting up to 40 K.

Scalable process

Batch manufacture of Si-based QD structures at prescribed locations, extremely low-cost and deterministic.

Applications

• Si-based quantum computing：Host spin qubits leveraging mature Si processes and long spin coherence times.
• Single-hole transistor logic：Enable ultra-low-power logic using single-hole transistors without high-res lithography.
• Low-dimensional quantum devices：Provide a platform for low-dimensional quantum confinement via in-situ QD formation.
• Si nanowire electronics：Integrate quantum-dot functionality into Si nanowire electronics.